The disclosure relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a semiconductor device having channels formed in a top-to-bottom direction (referred to herein as vertical channels).
To reduce size, semiconductor devices are designed to have vertical channels by disposing a source region and a drain region in the upper and lower parts of an active region.
FIGS. 1A and 1B are schematic cross-sectional views describing a method known to the inventors as being capable of fabricating a semiconductor device having vertical channels.
As shown in FIG. 1A, a plurality of gate hard mask patterns 12 are formed on a substrate 11, and pillar heads 13 are formed using the plurality of gate hard mask patterns as etch barriers or masks. Then, a sidewall passivation layer 14 is formed on sidewalls of each pillar head 13 and the respective gate hard mask pattern 12, and a pillar neck 15 is formed by isotropically etching the substrate 11 using the sidewall passivation layer 14 as an etch barrier or mask. The pillar neck 15 together with the pillar head 13 defines a pillar pattern.
Then, a gate insulation layer 16 is formed on a part of the pillar head 13 and the pillar neck 15, and a conductive layer 17 is deposited along the profile of the substrate.
As shown in FIG. 1B, a gate electrode 17A is formed to surround the pillar neck 15 by anisotropically etching the conductive layer 17.
In the known fabricating method, it is potential that the substrate 11 is partially lost as shown in the circle 18 of FIG. 1B during the anisotropic etching of the conductive layer 17. The potential loss of the substrate 11 deteriorates operation characteristics of the manufactured semiconductor device.
In particular, the anisotropic etching of the conductive layer 17 is performed until the sidewall passivation layer 14 formed at the side walls of the pillar head 13 is exposed. Thus, it is potential that the conductive layer 17 deposited between adjacent pillar patterns may be over-etched. Accordingly, a portion of the substrate 11 is potentially unintentionally lost as shown in the circle 18 of FIG. 1B.
Although an etching recipe having excellent selectivity may be used for the anisotropic etching of the conductive layer 17, there is still a limitation because the selectivity is not limitless.